1. Field of the Invention
The present invention relates to a display panel drive apparatus.
2. Description of the Related Art
In recent years, the development of display panels using light-emitting elements such as organic EL elements has advanced, and display apparatuses having such display panel mounted thereon are becoming popular. A drive apparatus and method for organic EL elements on a display panel is disclosed in, for example, Japanese Patent Application Kokai (Laid-Open) No. 2000-100563 (Reference 1). The drive apparatus of Reference 1 includes a switching device serially connected to an organic EL device and a control unit for switching periodically on and off the switching device, thereby periodically supplying a certain amount of drive current to the organic EL device. This drive apparatus reduces brightness drop due to the degradation of the organic EL device.
There are two methods of controlling display gradation employed by a current-output-type display panel driver (drive apparatus). One method changes mainly the value of a current for driving a display panel (hereinafter called a drive current) and another method is a PWM (Pulse Width Modulation) method that changes time during which to output the drive current. The PWM method has an advantage that for each output terminal, only one control signal is needed to control time during which to output the drive current. The drive current is usually controlled by a power supply voltage different from that for logic circuits so as to match characteristics of the display device. Accordingly, a level shift circuit needs to be inserted in each control signal path. Hence, the smaller number of control signals results in smaller chip area. The PWM method is widely used for its advantage.
FIG. 1 of the accompanying drawings shows a display panel 100. A cathode driver group 210 and an anode driver group 310 in combination drive the display panel 100. In the display panel 100, pixels 111 to 1mn are arranged in a matrix with m rows by n columns, where m and n are positive integers. For example, in the first row there are arranged pixels 111, 112, . . . , 11n, and in the mth row there are arranged pixels 1m1, 1m2, . . . , 1mn. The anode driver group 310 includes output drivers 310-1 to 310-n. The output driver 310-1 outputs a brightness pulse do_1 of drive current Ia_1 onto a data line DL1; the output driver 310-2 outputs a brightness pulse do_2 of drive current Ia_2 onto a data line DL2; . . . ; and the output driver 310-n outputs a brightness pulse do_n of drive current Ia_n onto a data line DLn.
When displaying an image on the screen, one of selection lines SL1 to SLm is selected by the cathode drivers 210-1 to 210-m, and the anode driver group 310 supplies the drive current to each of the pixels connected to (or arranged on) the selected select line. The figure shows the case where the output voltage level of the cathode driver 210-2 is at ‘L’ (low level) and thus pixels 121, 122, . . . , 12n arranged in the second row are selected. The output voltage levels of other drivers than the cathode driver 210-2 are at ‘H’ (high level), and the pixels other than those in the second row are not selected. At this time, the output driver 310-1 supplies drive current Ia_1 to pixel 121; the output driver 310-2 supplies drive current Ia_2 to pixel 122; . . . ; and the output driver 310-n supplies drive current Ia_n to pixel 12n. The pixel 121 lights with brightness corresponding to the drive current Ia_1. In the case of the PWM method, the output driver 310-1 changes the pulse width of the brightness pulse do_1, thereby changing the value of the drive current Ia_1 to control the display gradation of the pixel 121. The same applies to the pixels 122, . . . , 12n. 
FIG. 2 of the accompanying drawings shows a conventional display panel drive apparatus 300. The display panel drive apparatus 300 includes an output driver 310-i, where i is a positive integer from 1 to n, a current controlling voltage generating circuit 320, and a timing generating circuit 330. The display panel drive apparatus 300 usually includes a plurality of output drivers in addition to the output driver 310-i, but only the output driver 310-i is shown in the figure for simplicity of description. The display panel drive apparatus 300 uses current source circuits 311-i and 321 configured by MOS devices to obtain a constant current. The current source circuit 311-i has PMOS devices m1_i and m2_i. The source of the PMOS device m1_i is connected to a power supply voltage Vdd, and the drain thereof is connected to the source of the PMOS device m2_i. The drain of the PMOS device m2_i is connected to an output terminal 312-i, from which the brightness pulse do_i is output. A current control voltage ictrl from the current controlling voltage generating circuit 320 is applied to the gate of the PMOS device m1_i. The current control voltage ictrl is also applied commonly to the gate of the PMOS device of the current source circuit included in each of the other output drivers (not shown).
The current control voltage ictrl is generated by the current controlling voltage generating circuit 320. The circuit 320 includes the current source circuit 321, a current source 322, and an amplifier 323. The current source circuit 321 has PMOS devices m1_0 and m2_0. The source of the PMOS device m1_0 is connected to the power supply voltage Vdd, and the drain of the PMOS device m1_0 is connected to the source of the PMOS device m2_0. The drain of the PMOS device m2_0 is connected to the current source 322. The current control voltage ictrl from the amplifier 323 is applied to the gate of the PMOS device m1_0. The gate of the PMOS device m2_0 is connected to ground potential Vss. The amplifier 323 amplifies the drain voltage of the PMOS device m2_0 to apply the current control voltage ictrl to the gates of the PMOS device m1_i of the current source circuit 311-i included in the output driver 310-i and the PMOS device of the current source circuit included in each of (the) other output drivers (not shown) and also to the gate of the PMOS device m1_0 of the current source circuit 321 so that each drain current becomes equal to a reference current Iref.
The timing generating circuit 330 generates a PWM clock signal PC and a line trigger pulse signal LT and gives these signals to a drive pulse generating circuit 314-i included in the output driver 310-i. The PWM clock signal PC is used for each output driver to output a drive current corresponding to the gradation level #, and its clock pulse width is preset and invariable. The line trigger pulse signal LT is a signal for aligning output timings of the drive currents of the output drivers with each other. The timing generating circuit 330 also gives the PWM clock signal PC and the line trigger pulse signal LT to the drive pulse generating circuit included in each of the other output drivers (not shown).
The output driver 310-i includes the current source circuit 311-i, an output terminal 312-i, a data register 313-i, and the drive pulse generating circuit 314-i. The data register 313-i stores brightness data hd_i. The drive pulse generating circuit 314-i reads the brightness data hd_i from the data register 313-i and generates a drive pulse dd_i having a pulse width corresponding to the gradation level represented by the brightness data hd_i. The drive pulse generating circuit 314-i applies the drive pulse dd_i to the gate of the PMOS device m2_i. When the high-level drive pulse dd_i is applied to the gate of the PMOS device m2_i, the source-to-drain path is not electrically conductive. When the low-level drive pulse dd_i is applied, the source-to-drain path is rendered electrically conductive, and the brightness pulse do_i is generated from the output terminal 312-i. That is, the drive pulse dd_i is a signal for switching on/off the outputting of the brightness pulse do_i.
FIG. 3 of the accompanying drawings illustrates the operation waveforms of the display panel drive apparatus 300. Here, the number of gradation levels is 8 for simplicity of description. The drive pulse generating circuit 314-i starts outputting the low-level drive pulse dd_i at the time t0, i.e., when it receives a pulse of the line trigger pulse signal LT. The drive pulse generating circuit 314-i reads the brightness data hd_i from the data register 313-i and applies the low-level drive pulse dd_i to the gate of the PMOS device m2_i until the PWM clock period corresponding to the gradation level represented by the brightness data hd_i elapses. For example, if the gradation level represented by the brightness data hd_i is 1, the drive pulse generating circuit 314-i renders the drive pulse dd_i high in level at the time t1 (i.e., when the circuit 314-i receives a pulse of the PWM clock signal PC). The waveform of the drive pulse is indicated by dd_i (gradation level 1). If the gradation level represented by the brightness data hd_i is 6, the drive pulse generating circuit 314-i renders the drive pulse dd_i high in level at the time t3 (i.e., when the circuit 314-i receives six pulses of the PWM clock signal PC). The waveform of the drive pulse is indicated by dd_i (gradation level 6). Likewise, if the gradation level represented by the brightness data hd_i is 7, the drive pulse generating circuit 314-i renders the drive pulse dd_i high in level at the time t4, i.e., when the circuit 314-i receives seven pulses of the PWM clock signal PC. The waveform of the drive pulse is indicated by dd_i (gradation level 7).
When the low-level drive pulse dd_i is applied to the gate of the PMOS device m2_i, the source-to-drain path is rendered electrically conductive (i.e., ON), and the high-level brightness pulse do_i is output from the output terminal 312-i. For example, during the period from time t0 to t1, if the drive pulse of low level is applied to the gate of the PMOS device m2_i, the PMOS device m2_i is ON, and thus the brightness pulse do_i (gradation level 1) of high level is output from the output terminal 312-i during this time period. Likewise, if the drive pulse dd_i (gradation level 6) is applied to the gate of the PMOS device m2_i, the brightness pulse do_i (gradation level 6) is output, and if the drive pulse dd_i (gradation level 7) is applied, the brightness pulse do_i (gradation level 7) is output. Here, the amplitude of the brightness pulse do_i varies depending on the value of the current control voltage ictrl.